IEEE

Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients

Abstract: As CMOS device sizes continue to scale down, radiation-related reliability issues are of ever-growing concern. Single event double node upsets (SEDUs) in sequential logic and single event ...
mccormick.northwestern.edu

COMP_ENG 303: Advanced Digital Design

Overview of digital logic design. Implementation technologies, timing in combinational and sequential circuits, EDA tools, basic arithmetic units, introduction to simulation and synthesis using ...
IEEE

On-chip intrinsic evolution methodology for sequential logic circuit design

Abstract: This paper focuses on the application of Virtual Reconfigurable Circuit (VRC) design methodology and intrinsic evolution for the design of small sequential circuits and their implementation ...
GitHub

logic-circuit-design

Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course ...