EDN

Mentor Unveils FPGA Design-Flow Plans

WILSONVILLE, Ore.–May 19, 2003–Mentor Graphics Corporation announced a comprehensive field-programmable gate array (FPGA) design flow that expands traditional FPGA tools with new technologies to ...
EDN

Advanced FPGA Design Flow and Real-Time Measurement Solution

Agilent Technologies today announced that the Agilent EEsof EDA W1462 SystemVue FPGA Architect now supports on-board FPGA design and simulation with the Agilent M9703A AXIe wideband digital ...
Electronic Design

Agilent FPGA design flow supports AXIe digitizer

June 23, 2014. Agilent Technologies Inc. has announced that the Agilent EEsof EDA W1462 SystemVue FPGA Architect now supports on-board FPGA design and simulation with the Agilent M9703A AXIe wideband ...
New Electronics

Design exploration: changing the fpga design flow

FPGAs have undergone significant architectural changes in the last few years. Beginning with hard blocks such as ram and dsp, fpgas now also include transceivers and hard IP blocks, such as Ethernet ...
Electronic Design

FPGA Design Flow Takes Simulink Code Into Synthesis

Thanks to collaboration between The MathWorks and Mentor Graphics, MathWorks’ Simulink HDL Coder users gain a smooth path into synthesis. Mentor’s Precision Synthesis tool now supports HDL generated ...
Electronics Weekly

Mentor Graphics develops complete FPGA design flow

A complete FPGA design flow has been developed by Mentor Graphics, bringing together verification, synthesis, IP libraries and hardware/software co-design. Design entry can be in text, tabular or ...
Design-Reuse

A methodology for DSP-based FPGA design

FPGA use in DSP products is skyrocketing, and one only needs to look as far as the products into which DSP is deployed to understand why. Overall, DSP is becoming a highly ubiquitous technology, ...
Yahoo Finance

Blue Pearl Advances FPGA Design Automation, Announces Software Release With Enhanced Path Analysis

SAN JOSE, CA--(Marketwire - Oct 19, 2012) - Blue Pearl Software, Inc, the provider of EDA software that accelerates RTL signoff for FPGA designs, today, announced that it is shipping Release 6.1 of ...